______________________________________________________________________________________ 11

20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

Noise vs. Data Rate

The devices offer software-selectable internal oscillator

frequencies as well as software-selectable output data

rates. The LINEF bit in the CTRL1 register (Table 12)

determines the internal oscillator frequency. The RATE

bits in the command byte (Table 8) determine the ADC’s

output data rate. The devices also offer the option of

running in zero latency single-cycle conversion mode

(Table 2) or continuous conversion mode (Table 1). Set

SCYCLE = 0 in the CTRL1 register (Table 12) to run in

continuous conversion mode and SCYCLE = 1 for single-

cycle conversion mode.

Single-cycle conversion mode gives an output result with

no data latency. The devices output data up to 100sps

(2.048MHz internal oscillator) or 120sps (2.4576MHz

internal oscillator) with no data latency. In continuous

conversion mode, the output data rate is four times the

single-cycle conversion mode, for sample rates up to

400sps or 480sps. In continuous conversion mode, the

output data requires three additional 24-bit cycles to

settle from an input step.

Digital Filter

spectral nulls at the multiples of the data rate. For all

data rates less than 30sps, a spectral null occurs at the

line frequency of 60Hz and is guaranteed to attenuate

60Hz normal-mode components by more than 100dB.

Simultaneous 50Hz and 60Hz attenuation can be accom-

plished by using an external clock with a frequency of

2.25275MHz. This guarantees a minimum of 80dB rejec-

has a -3dB frequency equal to 24% of the data rate. See

Figures 1 and 2.

GPIOs

The devices provide four GPIO ports. When set as out-

puts, these digital I/Os can be used to drive the digital

inputs to a multiplexer or multichannel switch. Figure 3

details an example where four single-ended signals are

multiplexed in a break-before-make switching sequence,

using the MAX313, a quad SPST analog switch.

The devices’ GPIO ports are configurable through the

CTRL2 register. See Table 13. To select AIN1, write the

command to CTRL2 according to Table 4a. This selects

all GPIOs as outputs, as well as setting all logic signals

to 0 except the selected channel AIN1.

To select channel AIN3 next, it is a good idea to set all

switches to a high-impedance state first (see Table 4b).

Then select channel AIN3 by driving IN3 high (see

Table 4c).

Table 3a. Example of Self-Calibration

Table 3b. Example of System Calibration

STEP

DESCRIPTION

REGISTER

BIT

SCOC

SCGC

SOC

SGC

1

Initial power-up

0x000000

0x000000

0x000000

0x000000

1

1

1

1

2

Enable self-calibration registers

0x000000

0x000000

0x000000

0x000000

1

1

0

0

3

Self-calibration, DIN = 10010000

0x00007E 0xBFD345 0x000000

0x000000

1

1

0

0

STEP

DESCRIPTION

REGISTER

BIT

SCOC

SCGC

SOC

SGC

1

Initial power-up

0x000000

0x000000

0x000000

0x000000

1

1

1

1

2

Enable self-calibration registers

0x000000

0x000000

0x000000

0x000000

1

1

0

0

3

Self-calibration, DIN = 10010000

0x00007E 0xBFD345 0x000000

0x000000

1

1

0

0

4

Enable system offset register

0x00007E 0xBFD345 0x000000

0x000000

1

0

0

0

5

System-calibration offset, DIN = 1010000

0x00007E 0xBFD345 0xFFEE1D 0x000000

1

0

0

0

6

Enable system gain register

0x00007E 0xBFD345 0xFFEE1D 0x000000

0

0

0

0

7

System-calibration gain, DIN = 1011000

0x00007E 0xBFD345 0xFFEE1D 0x81CB5B

0

0

0

0