PT6552

V1.3

13

July 2010

OUTPUT PIN STATES DURING THE RESET PERIOD (WHEN /RES IS

LOW)

Output Pin

State During Reset

SG1/P1 to SG4/P4

L *1

SG5 to SG43

L

COM1, COM2

L

KS1/SG44, KS2/SG45

L *1

KS3 to KS5

X *2

KS6

H

DO

H *3

X: don’t care

Notes:

*1: These output pins are forcibly set to the segment output mode and held low.

*2: Immediately following power on, these output pins are undefined until the control data S0 and S1 has been sent.

*3: Since this output pin is an open-drain output, a pull-up resistor of between 1k and 10KΩ is required. This pin is held high during the reset period

even if key data is read.

NOTE ON CONTROLLER DISPLAY DATA TRANSFER

The PT6552 transfers the display data (D1 to D90) in two operations. To assure visual display quality, all the display data

should be sent within a 30ms or shorter period.