PIC18F2X datasheet(49/496 Pages) MICROCHIP

49 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 49

PIC18(L)F2X/4XK22

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTOSC

multiplexer while the primary clock is started. When the

primary clock becomes ready, a clock switch to the pri-

mary clock occurs (see Figure 3-3). When the clock

switch is complete, the HFIOFS or MFIOFS bit is

cleared, the OSTS bit is set and the primary clock is

providing the device clock. The IDLEN and SCS bits

are not affected by the switch. The LFINTOSC source

will continue to run if either the WDT or the Fail-Safe

Clock Monitor is enabled.

FIGURE 3-1:

TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 3-2:

TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

OSC1

Peripheral

Program

SOSCI

Counter

Clock

CPU

Clock

PC + 2

123

n-1

Clock Transition(1)

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

Q3 Q4

OSC1

Peripheral

Program

SOSC

PLL Clock

PC + 4

Output

CPU Clock

PC + 2

Clock

Counter

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 TOSC.

SCS<1:0> bits Changed

TPLL(1)

n-1 n

Clock

OSTS bit Set

Transition(2)

TOST(1)

TABLE 3-2:

INTERNAL OSCILLATOR FREQUENCY STABILITY BITS

IRCF<2:0>

INTSRC

MFIOSEL

INTOSC Stability Indication

000

MFIOFS = 0, HFIOFS = 0 LFINTOSC

000

MFIOFS = 0, HFIOFS = 1 HFINTOSC

000

MFIOFS = 1, HFIOFS = 0 MFINTOSC

010 or 001

MFIOFS = 0, HFIOFS = 1 HFINTOSC

010 or 001

MFIOFS = 1, HFIOFS = 0 MFINTOSC

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