LTM4618EVPBF datasheet(7/24 Pages) LINER

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LTM4618

4618f

NC (A1): No Connect. Leave ﬂoating.

FREQ (A2): Frequency Selection Pin. An internal low pass

ﬁlter is tied to this pin. The frequency can be selected from

250kHz to 780kHz by setting a voltage from this pin to

SGND. A programming resistor divider can be used to set

the operating frequency. See the Applications Information

section.

MODE/PLLIN (A3): Mode Selection or External Synchroni-

zation Pin. Tying this pin to INTVCC enables pulse-skipping

operation. Tying this pin low enables forced continuous

mode operation. Burst Mode operation is enabled by ﬂoat-

ing the pin. A clock on the pin will force the controller into

forced continuous mode of operation and synchronize to

the internal oscillator. The programming DC voltage has

to be removed for clock synchronization.

PGND (BANK 2: A4, B4, D4-D7, E1-E7, F1-F7, G1-G7,

H1-H7, J5-J7, K5, K7, L5-L7, M5-M7): Power ground

pins for both input and output returns.

VIN (BANK 1: A5-A7, B5-B7, C5-C7): Power Input Pins.

Apply input voltage between these pins and PGND pins.

Recommend placing input decoupling capacitance directly

between VIN pins and PGND pins.

TK/SS (B1): Output Voltage Tracking and Soft-Start Pin. An

internal soft-start current of 1.3μA charges the soft-start

capacitor. See the Applications Information section.

RUN (B2): Run Control Pin. A voltage above 1.35V on

this pin turns on the module. Forcing this pin below 1.1V

will shut down the output. The RUN pin has a 1μA pull-

up current source that increases to 10μA as the RUN pin

voltage reaches 1.5V and up to compliance. Therefore the

pin can be left ﬂoating for normal operation. A maximum

of 6V can be applied to the pin. A voltage divider can be

used for a UVLO function. See the Applications Informa-

tion section.

SGND (B3, C2 and C3): Signal Ground Pin. Return ground

path for all analog and low power circuitry. Tie a single

connection to PGND. See applications for details.

COMP (C1): Current control threshold and error ampli-

ﬁer compensation point. The module has been internally

compensated for most I/O ranges.

EXTVCC (C4): External Voltage Input. Bypasses the internal

INTVCC LDO and powers the internal circuitry and MOSFET

drivers. If a 5V source is available, the internal LDO is

disabled, and the power dissipation is lower, especially at

higher input voltages. See the Applications Information

section.

VFB (D1): The negative input of the error ampliﬁer. Inter-

nally, this pin is connected to VOUT with a 60.4kΩ precision

resistor. Different output voltages can be programmed

with an additional resistor between VFB and SGND pins.

See applications for details.

PGOOD (D2): Output Voltage Power Good Indicator. Open-

drain logic output that is pulled to ground when the output

voltage is not within ±7.5% of the regulation point.

INTVCC (D3): Internal 5V Regulator Output. This pin is for

additional decoupling of the 5V internal regulator.

VOUT (BANK 3: J1-J4, K1-K4, L1-L4, M1-M4): Power Out-

put Pins. Apply output load between these pins and PGND

pins. Recommend placing output decoupling capacitance

directly between these pins and PGND pins.

SW (K6): Switching Node of the Circuit. This pin is used

to check the switching frequency. Leave pin ﬂoating. A

resistor-capacitor snubber can be placed from SW to

PGND to eliminate high frequency switch node ringing.

See the Applications Information section.

PIN FUNCTIONS

BANK 1

VIN

SGND/PGND

CNTRL

BANK 3

BANK 2

PGND

VOUT

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