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SST25LF080A 데이터시트(PDF) 13 Page - Silicon Storage Technology, Inc

부품명 SST25LF080A
상세설명  8 Mbit SPI Serial Flash
PDF  25 Pages
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제조업체  SST [Silicon Storage Technology, Inc]
홈페이지  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST25LF080A 데이터시트(HTML) 13 Page - Silicon Storage Technology, Inc

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EOL Product Data Sheet
8 Mbit SPI Serial Flash
SST25LF080A
13
©2006 Silicon Storage Technology, Inc.
S71248-06-EOL
1/06
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
the any command sequence. The Sector-Erase instruction
is initiated by executing an 8-bit command, 20H, followed
by
address
bits
[A23-A0]. Address bits [AMS-A12]
(AMS = Most Significant address) are used to determine the
sector address (SAX), remaining address bits can be VIL or
VIH. CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status
register or wait TSE for the completion of the internal self-
timed Sector-Erase cycle. See Figure 8 for the Sector-
Erase sequence.
FIGURE 8: SECTOR-ERASE SEQUENCE
Block-Erase
The Block-Erase instruction clears all bits in the selected 32
KByte block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Block-Erase instruction is
initiated by executing an 8-bit command, 52H, followed by
address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most
significant address) are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
TBE for the completion of the internal self-timed Block-
Erase cycle. See Figure 9 for the Block-Erase sequence.
FIGURE 9: BLOCK-ERASE SEQUENCE
CE#
SO
SI
SCK
ADD.
01 2 3 4 5 6 7 8
ADD.
ADD.
20
HIGH IMPEDANCE
15 16
23 24
31
MODE 0
MODE 3
1248 F08.0
MSB
MSB
CE#
SO
SI
SCK
ADD.
01 2 3 4 5 6 7 8
ADD.
ADD.
52
HIGH IMPEDANCE
15 16
23 24
31
MODE 0
MODE 3
1248 F09.0
MSB
MSB



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