SST25WF080 datasheet(6/29 Pages) SST

6 / 29 page

Advance Information

8Mbit 1.8V SPI Serial Flash

SST25WF080

S71203-03-000

04/10

Hold

The Hold operation enables the hold pin functionality of the

RST#/HOLD# pin. Once set to hold pin mode, the RST#/

HOLD# pin continues functioning as a hold pin until the

device is powered off and then powered on. After a power-

off and power-on, the pin functionality returns to a reset pin

(RST#) mode. See “Enable-Hold (EHLD)” on page 18 for

detailed timing of the Hold instruction.

In the hold mode, serial sequences underway with the SPI

Flash memory are paused without resetting the clocking

sequence. To activate the HOLD# mode, CE# must be in

active low state. The HOLD# mode begins when the SCK

active low state coincides with the falling edge of the

HOLD# signal. The Hold mode ends when the rising edge

of the HOLD# signal coincides with the SCK active low

state. If the falling edge of the HOLD# signal does not coin-

cide with the SCK active low state, then the device enters

Hold mode when the SCK next reaches the active low

state. Similarly, if the rising edge of the HOLD# signal does

not coincide with the SCK active low state, then the device

exits Hold mode when the SCK next reaches the active low

state. See Figure 6 for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high-

impedance state while SI and SCK can be VIL or VIH.

If CE# is driven active high during a Hold condition, the

device returns to standby mode. The device can then be

re-initiated with the command sequences listed in Table 6.

As long as HOLD# signal is low, the memory remains in

the Hold condition. To resume communication with the

device, HOLD# must be driven active high, and CE# must

be driven active low. See Figure 6 for Hold timing.

FIGURE 6: Hold Condition Waveform

Write Protection

SST25WF080 provide software Write protection. The

Write Protect pin (WP#) enables or disables the lock-down

function of the status register. The Block-Protection bits

(BP3, BP2, BP1, BP0, and BPL) in the status register pro-

vide Write protection to the memory array and the status

Write Protect Pin (WP#)

The Write Protect (WP#) pin enables the lock-down func-

tion of the BPL bit (bit 7) in the status register. When WP#

is driven low, the execution of the Write-Status-Register

(WRSR) instruction is determined by the value of the BPL

bit (see Table 3). When WP# is high, the lock-down func-

tion of the BPL bit is disabled.

Active

Hold

Active

Hold

Active

1203 F05.0

SCK

HOLD#

TABLE

3: Conditions to execute Write-Status-Register (WRSR) Instruction

WP#

BPL

Execute WRSR Instruction

Not Allowed

Allowed

T3.0 1203

SST25WF080 데이터시트(PDF) 6 Page - Silicon Storage Technology, Inc

SST25WF080 데이터시트(HTML) 6 Page - Silicon Storage Technology, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

데이터시트 다운로드

링크 URL