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AT91SAM9M11 데이터시트(PDF) 21 Page - ATMEL Corporation |
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AT91SAM9M11 데이터시트(HTML) 21 Page - ATMEL Corporation |
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21 / 57 page ![]() 21 6437BS–ATARM–26-Apr-10 AT91SAM9M11 Figure 6-2. USB Selection 6.5 DMA Controller •Two Masters • Embeds 8 channels • 64 bytes/FIFO for Channel Buffering • Linked List support with Status Write Back operation at End of Transfer • Word, HalfWord, Byte transfer support. • memory to memory transfer • Peripheral to memory • Memory to peripheral The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below. The hardware interface numbers are also given below in Table HS Transceiver DMA HS USB DMA HS EHCI FS OHCI PA PB HS Transceiver 1 0 EN_UDPHS Table 6-7. DMA Channel Definition Instance Name T/R DMA Channel HW interface Number MCI0 TX/RX 0 SPI0 TX 1 SPI0 RX 2 SPI1 TX 3 SPI1 RX 4 SSC0 TX 5 SSC0 RX 6 SSC1 TX 7 SSC1 RX 8 AC97 TX 9 AC97 RX 10 MCI1 TX/RX 13 |
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