PIC18F23K22-ESLASHML datasheet(455/496 Pages) MICROCHIP

455 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 455

PIC18(L)F2X/4XK22

TABLE 27-18: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

100

THIGH

Clock High Time

100 kHz mode

4.0

—

s

Must operate at a minimum

of 1.5 MHz

400 kHz mode

0.6

—

s

Must operate at a minimum

of 10 MHz

SSP Module

1.5 TCY

—

101

TLOW

Clock Low Time

100 kHz mode

4.7

—

s

Must operate at a minimum

of 1.5 MHz

400 kHz mode

1.3

—

s

Must operate at a minimum

of 10 MHz

SSP Module

1.5 TCY

—

102

SDA and SCL Rise

Time

100 kHz mode

—

1000

400 kHz mode

20 + 0.1 CB

300

CB is specified to be from

10 to 400 pF

103

SDA and SCL Fall

Time

100 kHz mode

—

300

400 kHz mode

20 + 0.1 CB

300

CB is specified to be from

10 to 400 pF

TSU:STA Start Condition

Setup Time

100 kHz mode

4.7

—

s

Only relevant for Repeated

Start condition

400 kHz mode

0.6

—

s

THD:STA Start Condition

Hold Time

100 kHz mode

4.0

—

s

After this period, the first

clock pulse is generated

400 kHz mode

0.6

—

s

106

THD:DA

Data Input Hold

Time

100 kHz mode

—

400 kHz mode

0.9

s

107

TSU:DAT Data Input Setup

Time

100 kHz mode

250

—

(Note 2)

400 kHz mode

100

—

TSU:STO Stop Condition

Setup Time

100 kHz mode

4.7

—

s

400 kHz mode

0.6

—

s

109

TAA

Output Valid from

Clock

100 kHz mode

—

3500

(Note 1)

400 kHz mode

—

110

TBUF

Bus Free Time

100 kHz mode

4.7

—

s

Time the bus must be free

before a new transmission

can start

400 kHz mode

1.3

—

s

D102

Bus Capacitive Loading

—

400

Note 1:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement,

TSU:DAT

 250 ns, must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

standard mode I2C bus specification), before the SCL line is released.

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