21

FN2957.3

January 9, 2009

FIGURE 7B. BUS TIMING - MINIMUM MODE SYSTEM

NOTE:

Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the

second INTA cycle.

t4

t3

t2

t1

TW

TDVCL

TCLDX1 (7)

TWHDX

TCVCTX

TCHCTV (30)

TCLAV

TCLAZ

TCHCTV

(31) TCVCTX

TCVCTV

(17)

(26)

(27)

(29) TCVCTV

DATA OUT

AD15-AD0

INVALID ADDRESS

CLK (82C84A OUTPUT)

WRITE CYCLE

(

RD, INTA,

DT/

AD

15-AD0

DEN

WR

INTA CYCLE

(SEE NOTE)

(

AD

15-AD0

DT/

R

INTA

DEN

AD

15-AD0

SOFTWARE

HALT -

DEN, RD,

DT/

R = INDETERMINATE

SOFTWARE HALT

(29) TCVCTV

POINTER

TCL2CL1

(5)

t

W

TCLAV

TCLDV

TCLAX

(18)

TCLDX2

(29)

(28)

TWLWH

(38)

(29) TCVCTV

(19)

TCVCTX

(31)

(6)

(30)

(31)

(17)

TCH1CH2

(4)

80C86