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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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EP3C55 데이터시트(PDF) 16 Page - Altera Corporation |
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EP3C55 데이터시트(HTML) 16 Page - Altera Corporation |
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16 / 34 page  1–16 Chapter 1: Cyclone III Device Data Sheet Switching Characteristics Cyclone III Device Handbook, Volume 2 © January 2010 Altera Corporation f OUT (to global clock) PLL output frequency (–6 speed grade) — — 472.5 MHz PLL output frequency (–7 speed grade) — — 450 MHz PLL output frequency (–8 speed grade) — — 402.5 MHz t OUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % t LOCK Time required to lock from end of device configuration — — 1 ms t DLOCK Time required to lock dynamically (after switchover, reconfiguring any non-post-scale counters/delays or areset is deasserted) —— 1 ms t OUTJITTER_PERIOD_DEDC LK (5) Dedicated clock output period jitter F OUT ≥ 100 MHz —— 300 ps F OUT < 100 MHz ——30 mUI t OUTJITTER_CCJ _DEDCLK (5) Dedicated clock output cycle-to-cycle jitter F OUT ≥ 100 MHz —— 300 ps F OUT < 100 MHz ——30 mUI t OUTJITTER_PERIOD_IO (5) Regular I/O period jitter F OUT ≥ 100 MHz —— 650 ps F OUT < 100 MHz ——75 mUI t OUTJITTER_CCJ _IO (5) Regular I/O cycle-to-cycle jitter F OUT ≥ 100 MHz —— 650 ps F OUT < 100 MHz ——75 mUI t PLL_PSERR Accuracy of PLL phase shift — — ±50 ps t ARESET Minimum pulse width on areset signal. 10 — — ns t CONF IGPLL Time required to reconfigure scan chains for PLLs — 3.5 (6) — SCANCLK cycles f SC ANC LK scanclk frequency — — 100 MHz Notes to Table 1–20: (1) VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead. (2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (3) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. (4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps. (5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. (6) With 100 MHz scanclk frequency. Table 1–20. Cyclone III Devices PLL Specifications (Note 1) (Part 2 of 2) Symbol Parameter Min Typ Max Unit |
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