PCA2000_2001

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Product data sheet

Rev. 08 — 23 August 2010

7 of 30

NXP Semiconductors

PCA2000; PCA2001

32 kHz watch circuit with programmable adaptive motor pulse

The condition for a successful motor step is a positive step detection pulse (current in the

same direction as in the driving phase) followed by a negative detection pulse within a

given time limit. This time limit can be programmed between 3.9 ms and 10.7 ms (in steps

of 0.98 ms) in order to ensure a safe and correct step detection under all conditions (for

instance magnetic fields). The step detection phase stops after the last 31.25 ms, after the

start of the motor driving pulse.

7.3 Time calibration

The quartz crystal oscillator has an integrated capacitance of 5.2 pF, which is lower than

the oscillator frequency is typically 60 ppm higher than 32.768 kHz. This positive

frequency offset is compensated by removing the appropriate number of 8192 Hz pulses

in the divider chain (maximum 127 pulses), every 1 or 2 minutes. The time correction is

given in Table 3.

After measuring the effective oscillator frequency, the number of correction pulses must

be calculated and stored together with the calibration period in the OTP memory (see

Section 7.7).

Fig 6.

Step detection sequence and corresponding sampling voltage

mgw569

0.98 ms

(motor shorted)

sampling

voltage

sampling

voltage

positive detection level

negative detection level

programmable time limit

OTP C4 to C6

sampling

positive detection

negative detection

sampling results

motor shorted

sampling

61

μs

0.49 ms

t

t

t

Table 3.

Time calibration

Calibration

period

Correction per step (n = 1)

Correction per step (n = 127)

ppm

seconds per day ppm

seconds per day

1 minute

2.03

0.176

258

22.3

2 minutes

1.017

0.088

129

11.15