MRF24WB0MASLASHRM datasheet(15/34 Pages) MICROCHIP

15 / 34 page

 2010 Microchip Technology Inc.

DS70632A-page 15

MRF24WB0MA/MRF24WB0MB

2.3.4

STANDBY STATE

The Standby state is not user-controlled but is noted as

it helps identify and track certain operations of the

module during power tracing.

FIGURE 2-3:

MRF24WB0MA/MRF24WB0MB POWER-STATE DIAGRAM

2.4

JTAG Interface

Joint Test Action Group (JTAG) is the common name

used for the IEEE 1149.1 standard entitled Standard

Test Access Port and Boundary-Scan Architecture for

test access ports that are used for testing printed circuit

boards using boundary scan. The MRF24WB0MA/

MRF24WB0MB supports JTAG boundary scan. The

JTAG port provides the optional hardware JTAG Reset

input, JTAGRST. JTAG_EN and JTAGRST need to be

driven high to enable JTAG mode. JTAG should not be

enabled during normal functional operation. This func-

tion affects power state current.

2.5

Debug Serial Interface

The MRF24WB0MA/MRF24WB0MB incorporates a

Transmitted Data pin (DEBUGTX) and a Received Data

pin (DEBUGRX) for serial debugging purposes. These

pins can be connected to commercially available RS-

232 line drivers/receivers with appropriate external

level shifters. The serial interface is fully tested at

115200 bits/seconds with RS-232/UART interface

applications.

TABLE 2-1:

MRF24WB0MA/MRF24WB0MB POWER STATE DEFINITIONS

State

VDD

Description

Off

Power is completely disconnected

Hibernate

3.3V

All internal power regulators are OFF – enabled by HIBERNATE pin

Sleep

3.3V

Enabled by TCPIP driver

RX ON

3.3V

Receive circuits are on and receiving

TX ON

3.3V

Transmit circuits are on and transmitting

Standby

3.3V

State machine transition state only – not user controlled

Off

Hibernate

Standby

RX On

TX On

Sleep

200 us

10 us

Note 1

Note 1: See Section 2.2.

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