M48T37Y, M48T37V

Clock operations

Doc ID 7019 Rev 9

15/30

Figure 8.

Backup mode alarm waveforms

3.5

Calibrating the clock

The M48T37Y/V is driven by a quartz controlled oscillator with a nominal frequency of

32,768 Hz. The devices are tested not to exceed ±35 ppm (parts per million) oscillator

frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the

calibration bits properly set, the accuracy of each M48T37Y/V improves to better than

+1/–2 ppm at 25 °C.

The oscillation rate of any crystal changes with temperature (see Figure 10 on page 19).

Most clock chips compensate for crystal frequency and temperature shift error with

cumbersome trim capacitors. The M48T37Y/V design, however, employs periodic counter

correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure 11 on page 19. The number of times pulses

are blanked (subtracted, negative calibration) or split (added, positive calibration) depends

upon the value loaded into the five-bit calibration byte found in the control register. Adding

counts speeds the clock up, subtracting counts slows the clock down.

The calibration byte occupies the five lower order bits (D4-D0) in the control register 7FF8h.

These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the

sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs

within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one

second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125, 829, 120 (64 minutes x 60 seconds/minute x 32,768 cycles/second)

actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in

the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz,

each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds

per month which corresponds to a total range of +5.5 or –2.75 minutes per month.

AI03254B

VCC

IRQ/FT

tREC

VPFD (max)

VPFD (min)

ABE, AFE bit in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

HIGH-Z