PSD813F2 datasheet(101/128 Pages) STMICROELECTRONICS

101 / 128 page

PSD8XXFX

AC/DC parameters

Doc ID 7833 Rev 7

101/128

Figure 40.

Synchronous clock mode timing – PLD

tARPW

CPLD register clear

or preset pulse width

+ 20

tARD

CPLD array delay

Any

macrocell

+ 4

Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

Table 49.

CPLD combinatorial timing (3 V devices) (continued)

Symbol

Parameter

Conditions

-12

-15

-20

Aloc

Turbo

off

Slew

rate

(1)

Unit

Min Max Min Max Min Max

tCH

tCL

tCO

CLKIN

INPUT

REGISTERED

OUTPUT

AI02860

Table 50.

CPLD macrocell Synchronous clock mode timing (5 V devices)

Symbol

Parameter

Conditions

-70

-90

-15

Fast

Aloc

Turbo

off

Slew

rate

(1)

Unit

Min

Max

Min

Max

Min

Max

fMAX

Maximum

frequency

External

feedback

1/(tS+tCO)

40.0

30.30

25.00

MHz

Maximum

frequency

Internal

feedback (fCNT)

1/(tS+tCO–10)

66.6

43.48

31.25

MHz

Maximum

frequency

Pipelined data

1/(tCH+tCL)

83.3

50.00

35.71

MHz

Input setup time

+ 2

+ 10

Input hold time

tCH

Clock high time

Clock input

tCL

Clock low time

Clock input

tCO

Clock to output

delay

Clock input

– 2

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