STM706T/S/R, STM706P, STM708T/S/R

Operation

Doc ID 10518 Rev 10

11/33

3

Operation

3.1

Reset output

push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic high for

3.2

Push-button reset input

Figure 27) after it returns high. The MR input has an internal 40 k

Ω pull-up resistor, allowing

it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with

open-drain / collector outputs. Connect a normally open momentary switch from MR to GND

to create a manual reset function; external debounce circuitry is not required. If MR is driven

from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor

not used.

3.3

Watchdog input (STM706T/S/R and STM706P)

The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not

asserted. The internal 1.6s timer is cleared by either:

1.

a reset pulse, or

2.

by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.

See Figure 28 for STM706T/S/R and STM706P.

The timer remains cleared and does not count for as long as reset is asserted. As soon as

reset is released, the timer starts counting.

3.4

Watchdog output (STM706T/S/R and STM706P)

exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it

to the MR input.