CLC2000ISO8X datasheet(14/18 Pages) CADEKA

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Data Sheet

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These measurements are basic and are relatively easy to

perform with standard lab equipment. For design purposes

however, prior knowledge of actual signal levels and load

impedance is needed to determine the dissipated power.

Here, PD can be found from

PD = PQuiescent + PDynamic - PLoad

Quiescent power can be derived from the specified IS val-

ues along with known supply voltage, VSupply. Load power

can be calculated as above with the desired signal ampli-

tudes using:

(VLOAD)RMS = VPEAK / √2

( ILOAD)RMS = (VLOAD)RMS / Rloadeff

The dynamic power is focused primarily within the output

stage driving the load. This value can be calculated as:

PDYNAMIC = (VS+ - VLOAD)RMS × (ILOAD)RMS

Assuming the load is referenced in the middle of the pow-

er rails or Vsupply/2.

Figure 3 shows the maximum safe power dissipation in

the package vs. the ambient temperature for the 8 Lead

SOIC packages.

0.5

1.5

2.5

-40

-20

Ambient Temperature (°C)

SOIC-8

Figure 3. Maximum Power Derating

Better thermal ratings can be achieved by maximizing

PC board metallization at the package pins. However, be

careful of stray capacitance on the input pins.

In addition, increased airflow across the package can also

help to reduce the effective ӨJA of the package.

In the event of a short circuit condition, the CLC2000 has

circuitry to limit output drive capability to ±1000mA. This

will only protect against a momentary event. Extended

duration under these conditions will cause junction tem-

peratures to exceed 150°C. Due to internal metallization

constraints, continuous output current should be limited

to ±100mA.

Driving Capacitive Loads

Increased phase delay at the output due to capacitive load-

ing can cause ringing, peaking in the frequency response,

and possible unstable behavior. Use a series resistance,

RS, between the amplifier and the load to help improve

stability and settling performance. Refer to Figure 4.

Input

Output

Figure 4. Addition of RS for Driving

Capacitive Loads

Table 1 provides the recommended RS for various capaci-

tive loads. The recommended RS values result in <=1dB

peaking in the frequency response. The Frequency Re-

sponse vs. CL plots, on page 7, illustrates the response of

the CLC2000.

CL (pF)

RS (Ω)

-3dB BW (MHz)

275

24.5

250

175

100

13.5

135

500

1000

Table 1: Recommended RS vs. CL

For a given load capacitance, adjust RS to optimize the

tradeoff between settling time and bandwidth. In general,

reducing RS will increase bandwidth at the expense of ad-

ditional overshoot and ringing.

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