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STM690ADS6F 데이터시트(PDF) 14 Page - STMicroelectronics |
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STM690ADS6F 데이터시트(HTML) 14 Page - STMicroelectronics |
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14 / 43 page ![]() Operation STM690A/692A/703/704/802/805/817/818/819 14/43 Doc ID 10522 Rev 10 2.4 Backup battery switchover In the event of a power failure, it may be necessary to preserve the contents of external SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices automatically switch the SRAM to the backup supply when VCC falls. Note: When the battery is first connected without VCC power applied, the device does not immediately provide backup battery voltage on VOUT. Only after VCC exceeds VRST will the switchover operate as described below. This mode allows a battery to be attached during manufacturing but not used until after the system has been activated for the first time. As a result, no battery power is consumed by the device during storage and shipment. For the STM81x devices, the battery freshness seal can be initiated again by following the procedure outlined in Section 2.12. If the backup battery is not used, connect both VBAT and VOUT to VCC . Whenever VCC falls below the switchover voltage, VSO, VOUT is connected to VBAT through a 100 Ω switch. VSO is the lesser of VBAT and VRST. Choosing the lesser allows the device to be powered by VCC for as long as possible before switching over thereby maximizing the battery life. Assuming VBAT > 2.0 V, switchover at VSO ensures that battery backup mode is entered before VOUT gets too close to the 2.0 V minimum required to reliably retain data in most external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO point. VOUT is connected to VCC through a 3 Ω PMOS power switch. Note: The backup battery may be removed while VCC is valid, assuming VBAT is adequately decoupled (0.1 µF typ), without danger of triggering a reset. Table 4. I/O status in battery backup VOUT Connected to VBAT through internal switch VCC Disconnected from VOUT PFI Disabled PFO Logic low E High impedance ECON Logic high WDI Watchdog timer is disabled MR Disabled RST Logic low RST Logic high VBAT Connected to VOUT |
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