ST10F276Z5 datasheet(68/239 Pages) STMICROELECTRONICS

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Bootstrap loader

ST10F276Z5

68/239

5.6.6

Exiting alternate boot mode

Once the ABM mode is entered, it can be exited only with a software or hardware reset.

Note:

See note from Section 5.2.7 concerning software reset.

5.6.7

Alternate boot user software

If the rules described previously are respected (that is, mapping of variables, disabling of

interrupts, exit conditions, predefined vectors in Block 0 of Bank 2, Watchdog usage), then

users can write the software they want to execute in this mode starting from 09’0000h.

5.6.8

User/alternate mode signature integrity check

The behavior of the Alternate Boot mode is based on the computing of a signature between

the content of two memory locations and a comparison with a reference signature. This

requires that users who use Alternate Boot have reserved and programmed the Flash

memory locations according to:

User mode signature

00'0000h: memory address of operand0 for the signature computing

00’1FFCh: memory address of operand1 for the signature computing

00’1FFEh: memory address for the signature reference

Alternate mode signature

09'0000h: memory address of operand0 for the signature computing

09’1FFCh: memory address of operand1 for the signature computing

09’1FFEh: memory address for the signature reference

The values for operand0, operand1 and the signature should be such that the sequence

shown in the figure below is successfully executed.

MOV

Rx, CheckBlock1Addr; 00’0000h for standard reset

ADD

Rx, CheckBlock2Addr; 00’1FFCh for standard reset

CPLB

RLx

; 1s complement of the lower

; byte of the sum

CMP

Rx, CheckBlock3Addr; 00’1FFEh for standard reset

5.6.9

Alternate boot user software aspects

User defined alternate boot code must start at 09’0000h. A new SFR created on the

ST10F276Z5 indicates that the device is running in Alternate Boot mode: Bit 5 of EMUCON

(mapped at 0xFE0Ah) is set when the alternate boot is selected by the reset configuration.

All the other bits are ignored when checking the content of this register to read the value of

bit 5.

This bit is a read-only bit. It remains set until the next software or hardware reset.

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