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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST10F276Z5 데이터시트(PDF) 222 Page - STMicroelectronics |
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ST10F276Z5 데이터시트(HTML) 222 Page - STMicroelectronics |
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222 / 239 page  Electrical characteristics ST10F276Z5 222/239 23.8.21 External bus arbitration VDD = 5 V ±10%, VSS = 0 V, TA = -40 to +125 °C, CL = 50 pF Figure 66. External bus arbitration (releasing the bus) 1. The device completes the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64. Table 109. External bus arbitration Symbol Parameter FCPU = 40 MHz TCL = 12.5 ns Variable CPU Clock 1/2 TCL = 1 to 64 MHz Min. Max. Min. Max. t61 SR HOLD input setup time to CLKOUT 18.5 – 18.5 – ns t62 CC CLKOUT to HLDA high or BREQ low delay – 12.5 – 12.5 t63 CC CLKOUT to HLDA low or BREQ high delay t64 CC CSx release 1 20 20 t65 CC CSx drive – 4 15 – 4 15 t66 CC Other signals release 1 –20 – 20 t67 CC Other signals drive – 4 15 – 4 15 t61 t63 t66 (1) t64 1) 2) t62 3) CLKOUT HOLD HLDA BREQ Others CSx (P6.x) |
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