STW4811MBRATSLASHLF datasheet(42/85 Pages) STMICROELECTRONICS

42 / 85 page

Functional description

STw4811M/STw4811N

42/85

CD00131784

Main features

●

Fixed 1.8 V output voltage

●

Two power domains:

–

‘High power mode’ when multimedia processor is in run mode - 600 mA full load

–

‘Low current mode’ when multimedia processor is in sleep mode, 5 mA current

capability.

Fast switching from low current to high power mode.

The regulator is in ‘low current mode’ when multimedia processor is in sleep

mode. PWREN signal indicates that the multimedia processor is about to switch to

run mode. VDDOK signal indicates to the multimedia processor that all supplies

are in the specified range.

Note:

The definition of sleep mode is given in 4.2.3: Sleep mode section.

●

Soft start circuitry at start up, from power off to high power mode, when PON ball

changes from “0” to “1”.

4.3.4

VPLL

This LDO is dedicated to the multimedia processor PLL (1.05, 1.2, 1.3, 1.8 V) power supply

with 10 mA max full load (

power control registers - Table 23 and Table 24).

Main features

●

Programmable output voltage, ‘vpll_sel[1:0]’ bits of

power control register - Table 23

and

Table 24)

●

Two power domains:

–

‘High power mode’ 10 mA full load

–

‘Power down mode’ or ‘standby mode’ when regulators are switched off and there

is no power consumption (‘en_vpll’ bit of

power control register - Table 24)

●

Soft start circuitry at start up, from power off to high power mode, when PON ball

changes from “0” to “1”.

4.3.5

VANA

This LDO is dedicated to the multimedia processor analog function (2.5 V) power supply

with 10 mA full load.

Main features:

●

2.5 V output voltage,

●

Two power domains

–

‘High power mode’ 10 mA full load

–

‘Power down mode’ or ‘standby mode’ when regulators are switched off and there

is no power consumption (‘en_vana’ bit of

power control register - Table 25),

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