M95256-CS3GSLASHK datasheet(6/48 Pages) STMICROELECTRONICS

6 / 48 page

Description

M95256-DR, M95256, M95256-W, M95256-R

6/48

Doc ID 12276 Rev 11

Description

The M95256, M95256-W, M95256-R and M95256-DR are electrically erasable

programmable memory (EEPROM) devices. They are accessed by a high speed SPI-

compatible bus. Their memory array is organized as 32768 × 8 bits.

The M95256-DR also offers an additional page, named the Identification Page (64 bytes)

which can be written and (later) permanently locked in Read-only mode. This Identification

Page offers flexibility in the application board production line, as the Identification Page can

be used to store unique identification parameters and/or parameters specific to the

production line.

The device is accessed by a simple serial interface that is SPI-compatible.

Figure 1.

Logic diagram

The bus signals are C, D and Q, as shown in Table 1 and Figure 1.

The device is selected when Chip Select (S) is taken low. Communications with the device

can be interrupted using Hold (HOLD).

Figure 2.

8-pin package connections

See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.

Caution:

As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet

(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by

ST Microelectronics must never be exposed to UV light.

AI12361

VCC

M95256

HOLD

VSS

HOLD

SVCC

AI12362

M95256

M95256-CS3G/K 데이터시트(PDF) 6 Page - STMicroelectronics