IP1206PBF datasheet(27/30 Pages) IRF

27 / 30 page

2/26/2008

www.irf.com

iP1206PbF

Fig. 27 Top component and via placement (Topside, transparent view down)

PCB Layout Guidelines

The following guidelines are recommended to reduce the parasitic values and optimize overall performance.

• All pads on the iP1206 footprint design need to be Solder-mask defined (see Figure 26).

Also refer to

International Rectifier application notes AN1028 and AN1029 for further footprint design guidance.

• Place as many vias around the Power pads (VIN, VSW, and PGND) for both electrical and optimal thermal

performance.

• Vias in between the different power pads may overlap the pad opening and solder mask edge without the need

to plug the via hole. Vias with a 13mil drill hole and 25mil capture pad were used in this example.

• A minimum of six 10µF, X5R, 16V ceramic capacitors per iP1206 are recommended for the lowest loss due to

input capacitor ESR.

• Placement of the ceramic input capacitors is critical to optimize switching performance. In cases where there is

a space constraint on the top layer capacitors C3,C4, C7 and C8 can be placed on the bottom layer directly

below the footprints of C1, C2, C5 and C6.

• Dedicate at least two layers for PGND only.

• Duplicate the Power Nodes on multiple layers (refer to AN1029).

• Refer to AN-1030 for information on applying IPOWIR products in your thermal environment for Safe Operation.

IP1206PBF 데이터시트(PDF) 27 Page - International Rectifier