Data Sheet TLE 6220 GP

V2.1

Page

2007-05-03

7

SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6220 GP.

The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while

the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of

serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select

CS

makes any transition.

SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI informa-

tion is read in on the falling edge of SCLK. Input data is latched in the shift register and then

transferred to the control buffer of the output stages.

The input data consists of one byte, made up of four control bits and four data bits. The control

word is used to program the device, to operate it in a certain mode as well as providing diag-

nostic information (see page 11). The four data bits contain the input information for the four

channels, and are high active.

SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant

bit first. SO is in a high impedance state until the

nostic data will appear at the SO pin following the rising edge of SCLK.

switches all outputs OFF. An internal pull-up structure is provided on chip. As long as the reset

pin is low the device is in low quiescent current mode and the supply current is reduced to typ.

20µA.

Output Stage Control

The four outputs of the TLE 6220 GP can either be controlled in parallel (IN1...IN4), or via the

Serial Peripheral Interface (SPI).

Parallel Control

A Boolean operation (either AND or OR) is performed on each of the parallel inputs and re-

spective SPI data bits, in order to determine the states of the respective outputs. The type of

Boolean operation performed is programmed via the serial interface.

The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins

are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4

are switched OFF. PRG pin itself is internally pulled up when it is not connected.

PRG - Program pin.

Parallel inputs Channel 1 to 4 are high active

PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active.