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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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S9S08QD2CSC 데이터시트(PDF) 29 Page - Freescale Semiconductor, Inc |
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S9S08QD2CSC 데이터시트(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 198 page  Chapter 3 Modes of Operation MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 29 3.6.4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the LVD is enabled. 3.6.5 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2 Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes. Table 3-2. BDM Enabled Stop Mode Behavior Mode PPDC CPU, Digital Peripherals, Flash RAM ICS ADC1 Regulator I/O Pins RTI Stop3 0 Standby Standby Active Optionally on Active States held Optionally on Table 3-3. LVD Enabled Stop Mode Behavior Mode PPDC CPU, Digital Peripherals, Flash RAM ICS ADC1 Regulator I/O Pins RTI Stop3 0 Standby Standby Off1 1 ICS can be configured to run in stop3. Please see the ICS registers. Optionally on Active States held Optionally on Table 3-4. Stop Mode Behavior Peripheral Mode Stop2 Stop3 CPU Off Standby RAM Standby Standby Flash Off Standby Parallel Port Registers Off Standby ADC1 Off Optionally On1 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. ICS Off Standby TPM1 & TPM2 Off Standby Voltage Regulator Standby Standby I/O Pins States Held States Held |
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