KMPC8567CVTAUGGA datasheet(83/139 Pages) FREESCALE

83 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Serial RapidIO

For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the

transmitter shall fall entirely within the unshaded portion of the Transmitter Output Compliance Mask

shown in Figure 53 with the parameters specified in Table 60 when measured at the output pins of the

device and the device is driving a 100 Ohm +/–5% differential resistive load. The output eye pattern of an

LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol

interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is

disabled or minimized.

Figure 53. Transmitter Output Compliance Mask

Table 59. Long Run Transmitter AC Timing Specifications—3.125 GBaud

Characteristic

Symbol

Range

Unit

Notes

Min

Max

Output Voltage,

–0.40

2.30

Volts

Voltage relative to COMMON

of either signal comprising a

differential pair

Differential Output Voltage

VDIFFPP

800

1600

mV p-p

—

Deterministic Jitter

—

0.17

UI p-p

—

Total Jitter

—0.35

UI p-p

—

Multiple output skew

SMO

—

1000

Skew at the transmitter output

between lanes of a multilane

link

Unit Interval

320

+/– 100 ppm

VDIFF min

VDIFF max

-VDIFF min

-VDIFF max

1-B

Time in UI

A1-A

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