MSC8102 datasheet(21/80 Pages) FREESCALE

21 / 80 page

Memory Controller Signals

MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

1-11

ALE

Output

Address Latch Enable

Controls the external address latch used in an external master bus.

PWE[0–3]

PSDDQM[0–3]

PBS[0–3]

Output

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for

write operations.

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory

operations. The timing of these pins is programmed in the UPM. The actual driven value depends on

the address and size of the transaction and the port size of the accessed device.

PSDA10

PGPL0

Output

System Bus SDRAM A10

From the bus SDRAM controller. The precharge command defines which bank is precharged. When

the row address is driven, it is a part of the row address. When column address is driven, it is a part

of column address.

System Bus UPM General-Purpose Line 0

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PSDWE

PGPL1

Output

System Bus SDRAM Write Enable

From the bus SDRAM controller. Should connect to SDRAM WE input.

System Bus UPM General-Purpose Line 1

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

POE

PSDRAS

PGPL2

Output

System Bus Output Enable

From the bus GPCM. Controls the output buffer of memory devices during read operations.

System Bus SDRAM RAS

From the bus SDRAM controller. Should connect to SDRAM RAS input.

System Bus UPM General-Purpose Line 2

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PSDCAS

PGPL3

Output

System Bus SDRAM CAS

From the bus SDRAM controller. Should connect to SDRAM CAS input.

System Bus UPM General-Purpose Line 3

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PGTA

PUPMWAIT

PGPL4

PPBS

Input

Output

System GPCM TA

Terminates external transactions during GPCM operation. Requires an external pull-up resistor for

proper operation.

System Bus UPM Wait

An external device holds this pin low to force the UPM to wait until the device is ready to continue the

operation.

System Bus UPM General-Purpose Line 4

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

System Bus Parity Byte Select

In systems that store data parity in a separate chip, this output is used as the byte-select for that

chip.

Table 1-6.

Memory Controller Signals (Continued)

Signal Name

Type

Description

MSC8102 데이터시트(PDF) 21 Page - Freescale Semiconductor, Inc

MSC8102 데이터시트(HTML) 21 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

데이터시트 다운로드

링크 URL