MSC8151 datasheet(60/68 Pages) FREESCALE

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MSC8151 Single-Core Digital Signal Processor Data Sheet, Rev. 1

Hardware Design Considerations

Freescale Semiconductor

3.5.1.2

DDR Interface Is Used With 32-Bit DDR Memory Only

Table 41 lists unused pin connection when using 32-bit DDR memory. The 32 most significant data lines are not used.

3.5.1.3

ECC Unused Pin Connections

When the error code correction mechanism is not used in any 32- or 64-bit DDR configuration, refer to Table 42 to determine

the correct pin connections.

Table 41. Connectivity of DDR Related Pins When Using 32-bit DDR Memory Only

Signal Name

Pin Connection

MDQ[31–0]

in use

MDQ[63–32]

MDQS[3–0]

in use

MDQS[7–4]

MDQS[3–0]

in use

MDQS[7–4]

MA[15–0]

in use

MCK[2–0]

in use

MCK[2–0]

in use

MCS[1–0]

in use

MDM[3–0]

in use

MDM[7–4]

MBA[2–0]

in use

MCAS

in use

MCKE[1–0]

in use

MODT[1–0]

in use

MMDIC[1–0]

in use

MRAS

in use

MWE

in use

MVREF

in use

GVDD1/GVDD2

in use

Notes:

For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is not used.

For MSC8151 Revision 1 silicon, these pins were connected to GND (or VDD). For newer revisions of the MSC8151,

connecting these pins to GND increases device power consumption.

Table 42. Connectivity of Unused ECC Mechanism Pins

Signal Name

Pin connection

MECC[7–0]

MDM8

MDQS8

Notes:

For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is not used.

For MSC8151 Revision 1 silicon, these pins were connected to GND (or VDD). For newer revisions of the MSC8151,

connecting these pins to GND increases device power consumption.

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