MSC8252 datasheet(49/68 Pages) FREESCALE

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Electrical Characteristics

MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Freescale Semiconductor

Figure 26 provides the AC test load for the SPI.

Figure 26. SPI AC Test Load

Figure 27 and Figure 28 represent the AC timings from Table 36. Note that although the specifications generally reference the

rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

Figure 27 shows the SPI timings in slave mode (external clock).

Figure 27. SPI AC Timing in Slave Mode (External Clock)

Figure 28 shows the SPI timings in master mode (internal clock).

Figure 28. SPI AC Timing in Master Mode (Internal Clock)

SPI inputs—Master mode (internal clock) input hold time

tNIIXKH

0—

—

SPI inputs—Slave mode (external clock) input setup time

tNEIVKH

4—

—

SPI inputs—Slave mode (external clock) input hold time

tNEIXKH

2—

—

Notes:

The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until

outputs (O) are invalid (X).

Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal.

Timings are measured at the pin.

Table 36. SPI AC Timing Specifications

Parameter

Symbol 1

Min

Max

Unit

Note

Output

Z0 = 50 Ω

VDDIO/2

RL = 50 Ω

SPICLK (input)

tNEIXKH

tNEKHOV

Input Signals:

SPIMOSI

(See note)

Output Signals:

SPIMISO

(See note)

tNEIVKH

tNEKHOX

Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0

SPICLK (output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See note)

Output Signals:

SPIMOSI

(See note)

tNIIVKH

tNIKHOX

Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0

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