M41T66

Clock operation

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3.7

Output driver pin

When the OFIE bit, AFE bit, and watchdog register are not set to generate an interrupt, the

IRQ/OUT pin becomes an output driver that reflects the contents of D7 of the calibration

register. In other words, when D7 (OUT bit) is a '0,' then the IRQ/OUT pin will be driven low.

Note:

The IRQ/OUT pin is an open drain which requires an external pull-up resistor.

3.8

Oscillator stop detection

If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either

stopped, or was stopped for some period of time and can be used to judge the validity of the

clock and date data. This bit will be set to '1' any time the oscillator stops.

In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the

STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the

oscillator.

The following conditions can cause the OF bit to be set:

●

The first time power is applied (defaults to a '1' on power-up).

●

●

The ST bit is set to '1.'

●

External interference of the crystal

If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ/OUTpin will also be

activated. The IRQ/OUT output is cleared by resetting the OFIE or OF bit to '0' (NOT by

reading the flag register).

The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have

run for at least 1 second before attempting to reset the OF bit to '0.' If the trigger event

occurs during a power-down condition, this bit will be set correctly.