M48T201Y datasheet(11/37 Pages) STMICROELECTRONICS

11 / 37 page

M48T201Y, M48T201V

Operation

11/37

Table 2.

Operating modes

Note:

X = VIH or VIL; VSO = battery backup switchover voltage

2.2

Read mode

The M48T201Y/V executes a READ cycle whenever W (WRITE enable) is high and E (chip

enable) is low. The unique address specified by the address inputs (A0-A18) defines which

one of the on-chip TIMEKEEPER® registers or external SRAM locations is to be accessed.

When the address presented to the M48T201Y/V is in the range of 7FFFFh-7FFF0h, one of

the on-board TIMEKEEPER registers is accessed and valid data will be available to the

eight data output drivers within tAVQV after the address input signal is stable, providing that

the E and G access times are also satisfied. If they are not, then data access must be

measured from the latter occurring signal (E or G) and the limiting parameter is either tELQV

for E or tGLQV for G rather than the address access time. When one of the on-chip

TIMEKEEPER registers is selected for READ, the GCON signal will remain inactive

throughout the READ cycle.

When the address value presented to the M48T201Y/V is outside the range of

TIMEKEEPER registers, an external SRAM location will be selected. In this case the G

signal will be passed to the GCON pin, with the specified delay times of tAOEL or tOERL.

Figure 4.

GCON timing when switching between RTC and external SRAM

Mode

VCC

DQ7-

DQ0

Power

Deselect

4.5 V to 5.5 V

3.0 V to 3.6 V

VIH

High-Z

Standby

WRITE

VIL

XVIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High-Z

Active

Deselect

VSO to VPFD (min)

(1)

See Table 14 on page 30 for details.

High-Z

CMOS standby

Deselect

≤ VSO(1)

High-Z

Battery backup

AI02333

GCON

tAOEL

ADDRESS

00000h - 7FFEFh

7FFF0h - 7FFFFh

00000h - 7FFEFh

7FFF0h - 7FFFFh

tAOEH

tOERL

tRO

External SRAM

RTC

External SRAM

RTC

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