M48Z129Y, M48Z129V

Operation modes

Doc ID 5716 Rev 7

9/20

2.2

WRITE mode

The M48Z129Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)

are active. The start of a WRITE is referenced from the latter occurring falling edge of W or

E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held

should be kept high during WRITE cycles to avoid bus contention; although, if the output

W falls.

Figure 6.

WRITE enable controlled, WRITE mode AC waveform

Figure 7.

Chip enable controlled, WRITE mode AC waveforms

AI02382

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A16

E

W

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI03611

tAVAV

tEHAX

tDVEH

DATA INPUT

A0-A16

E

W

DQ0-DQ7

VALID

tAVEH

tAVEL

tWLWH

tAVWL

tEHDX

tELEH