IC-MLEVALML1D datasheet(2/17 Pages) ICHAUS

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iC-ML

HALL Position Sensor / Encoder

Rev A3, Page 2/17

DESCRIPTION

The CMOS device iC-ML consists of four hall sen-

sors arranged in a line and optimized to read out

magnetic tapes with 2.56 mm pole spacing.

This

sensor array permits error-tolerant adjustment of the

magnetic tape, reducing assembly efforts. The inte-

grated signal conditioning unit provides a differential

sine/cosine signal at the output.

The sensor generates one sine/cosine cycle for each

full magnetic periode of 5.12 mm, enabling the trav-

elling distance to be clearly determined. At the same

time the internal amplitude control unit produces an

regulated output amplitude of 2 Vpp regardless of

variations in the magnetic ﬁeld strength, supply volt-

age and temperature. Furthermore, signals are pro-

vided which enable the sensor amplitude to be as-

sessed and also report any magnetic tape loss.

With the aid of the integrated 8-bit sine/digital con-

verter the travelling distance within a magnetic peri-

ode is determined from the sine/cosine signals. This

is output via an incremental interface in a number

of selectable resolutions. The zero position of each

periode is indicated by an index pulse. The maxi-

mum resolution of 8-bit is maintained up to travelling

speeds of 5 m/s.

The absolute position within a magnetic periode can

be converted back to a linear analog output signal

using the internal D/A converter; here, output volt-

age limits can be set as required using the external

pins. Either a periodic linear signal (sawtooth) or a

delta voltage (triangle) can be provided. iC-ML can

be easily cascaded in three different modes of chain

operation so that several axes of transistion can be

scanned. The linear positions of the individual axes

can then be read via a common bus.

Used in conjunction with a magnetic tape iC-ML can

act as an linear encoder system with an integrated

magnetic scanning feature.

PACKAGES TSSOP20

PIN CONFIGURATION - TSSOP20

PIN FUNCTIONS

No. Name Function

1 T0

Test Pin (connect to GND)

2 NEN

Enable Input, low active

3 n.c.

4 GND

Ground

5 n.c.

6 CFG2 Conﬁguration Input 2

7 B

Bidirectional Input/Output B

8 n.c.

9 A

Bidirectional Input/Output A

10 n.c.

11 VTC

Test Pin (do not connect)

12 D

Bidirectional Input/Output D

13 n.c.

14 C

Bidirectional Input/Output C

15 CFG3 Conﬁguration Input 3

16 n.c.

17 VDD

+5 V Supply Voltage

18 n.c.

19 CFG1 Conﬁguration Input 1

20 VTS

Test Pin (do not connect)

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