FX589P datasheet(5/18 Pages) CMLMICRO

5 / 18 page

Application Information ......

Fig.4 Minimum µController System Connections

Note the device operation is not guaranteed

above 64,000 bits/s or below 4,000 bits/s at

the relevant supply voltage

Table 1 Clock/Data Rates

* V

DD >= 4.5V

A division ratio to facilitate data-rate setting is

controlled by the logic level inputs on the ClkDivA/B

pins, and is shown in Table 1 (below) - together with

examples of how various ‘standard’ data-rates may be

derived from common µP or Xtal frequencies.

Data Rate =

Xtal/Clock Frequency

Division Ratio (ClkDivA/B)

FX589

GMSK MODEM

CIRCUITS

Rx DATA

Rx CLOCK

Tx DATA

Tx CLOCK

Tx OUT

SIGNAL AND

DC LEVEL

ADJUSTMENT

SIGNAL AND

DC LEVEL

ADJUSTMENT

Rx SIGNAL IN

Rx FEEDBACK

Rx FREQUENCY

DISCRIMINATOR

RxD

RxC

TxD

TxC

µCONTROLLER

or UART

FREQUENCY

MODULATOR

Fig.3 External Signal Paths

Clock Oscillator and Dividers

The Tx and (nominal) Rx data rates are determined

by division of the frequency present at the Xtal pin,

which may be generated by the on-chip Xtal oscillator

or be derived from an external source. Any Xtal/clock

frequency in the range 1.0MHz to 5.0MHz (V

DD = 3.0V)

or 1.0MHz to 8.2MHz (V

DD = 5.0V) may be employed,

depending upon the desired data rate.

Xtal/Clock Frequency (MHz)

8.192

4.9152

4.096

2.4576

2.048

[12.288/3]

[12.288/5]

[6.144/3]

Inputs

Division Ratio:

ClkDiv ClkDiv

Xtal Freq

Data Rate (b/s)

Data Rate

128

64000*

38400*

32000

19200

16000

256

32000

19200

16000

9600

8000

512

16000

9600

8000

4800

4000

1024

8000

4800

4000

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