4-Level FSK Modem Data Pump

FX919A

© 1996 Consumer Microcircuits Limited

22

D/919A/4

RRC Filter Delay

The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the

input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through

to the RRC filter in both transmit and receive modes, as illustrated below:

Symbol-times

Tx Symbol to RRC Filter

Rx Symbol to De-interleave Buffer

Tx Symbol at Txop pin / Rx Symbol from FM discriminator

Figure 12 RRC Low Pass Filter Delay

1.5.5.3

Control Register

This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock

extraction and signal level measurement circuits and the Frame Sync pattern recognition tolerance.

Control Register B7, B6: CKDIV - Clock Division Ratio

These bits control a frequency divider driven from the clock signal present at the XTALN pin, and hence

determine the nominal symbol rate. The table below shows how symbol rates of 2400/4800/9600 symbols/sec

may be obtained from common Xtal frequencies:

Xtal Frequency (MHz)

2.4576

4.9152

9.8304

B7

B6

Division Ratio:

Xtal Frequency/Symbol Rate

Symbol Rate (symbols/sec)

0

0

512

4800

9600

0

1

1024

2400

4800

9600

1

0

2048

2400

4800

1

1

4096

2400

Note: Device operation is not guaranteed below 2400 or above 9600 symbols/sec.