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FX949 데이터시트(PDF) 12 Page - CML Microcircuits |
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FX949 데이터시트(HTML) 12 Page - CML Microcircuits |
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12 / 25 page ![]() CDPD Wireless Modem Data Pump FX949 © 1996 Consumer Microcircuits Limited 12 D/949/5 IRQ FLAGS Register (Hex address $50) This is a read only register that contains flags to indicate the source of an interrupt, as described below: SYNCF (Bit 7) This bit is set to "1" when the device has decoded the sync word on the forward channel. It also is set to "1" if, after detecting sync, it fails to detect it 420 bits later, indicating sync has been lost. The state of sync can be read from the STATUS register. This bit is reset to "0" after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated, depending on the state of the IRQ MASK register. DECF (Bit 6) This bit is set to "1" when the decode status of the Mobile Data Base Station (MDBS) in the forward channel changes state. The decode state can be read from the STATUS register. This bit is reset to "0" after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated depending on the state of the IRQ MASK register. IDLEF (Bit 5) This bit is set to "1" when the idle status of the Mobile Data Base Station (MDBS) in the forward channel changes state. The idle state can be read from the STATUS register. This bit is reset to "0" after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated depending on the state of the IRQ MASK register. TXF (Bit 4) This bit is used in transmission of data from the 47 symbol "write only" buffer on the reverse channel. This bit is set to "1" when the buffer is empty and new data can be loaded in. It is reset to "0" after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated depending on the state of the IRQ MASK register. TIMEF (Bit 3) This bit is set to "1" when the timer expires and it is reset after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated depending on the state of the IRQ MASK register. Write Only Registers A0 - A6 HEX ADDRES S RDN WRN CSN REGISTER NAME BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) BIT 4 (D4) BIT 3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0) $00 1 0 0 TX DATA 0 X X <------------------- DATA SYMBOL 0 -------------------> $01 1 0 0 TX DATA 1 X X <------------------- DATA SYMBOL 1 -------------------> $02 1 0 0 TX DATA 2 X X <------------------- DATA SYMBOL 2 -------------------> | | | | | | | | | | | | $2C 1 0 0 TX DATA 44 X X <------------------- DATA SYMBOL 44 ------------------> $2D 1 0 0 TX DATA 45 X X <------------------- DATA SYMBOL 45 ------------------> $2E 1 0 0 TX DATA 46 X X <------------------- DATA SYMBOL 46 ------------------> $2F 1 0 0 TIMER <------------------------------- 0 TO 255 SECONDS ----------------------------> $30 1 0 0 CONTROL ACQ RX- HOLD PSRX PSTX CI <--SYNC ERROR LIMIT---> (SERL) $31 1 0 0 IRQ MASK SYNCM DEC M IDLEM TXM TIMEM ERR M 0 0 |
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