Symbol

Parameter

Conditions

Min

Typ

Max

Units

OVER CURRENT

V

OFFSET

Comparator Voltage Offset

-5

0

5

mV

I

CS-

Current Limit Offset Current

V

9.5

10.0

10.5

µA

GATE DRIVE

R

DSON1

High-Side FET Driver Pull-Up On

Resistance

V

+100 mA

1.7

Ω

R

DSON2

High-Side FET Driver Pull-Down On

Resistance

V

-100 mA

1.2

Ω

R

DSON3

Low-Side FET Driver Pull-Up On

Resistance

V

1.7

Ω

R

DSON4

Low-Side FET Driver Pull-Down On

Resistance

V

1.0

Ω

T

DT

Deadtime Timeout

F

40

ns

SOFT-START

I

SS

Soft-Start Source Current

V

2

3

4

µA

R

SS_PD

Soft-Start Pull-Down Resistance

V

288

Ω

T

SS_INT

Internal Soft-Start Time

1.28

ms

POWERGOOD

I

PGS

PGOOD Low Sink Current

V

60

100

µA

I

PGL

PGOOD Leakage Current

V

1

10

µA

O

VT

Over-Voltage Threshold

V

114

117

120

%

O

VT_HYS

O

V

2

%

U

VT

Under-Voltage Threshold

V

91

94

97

%

U

VT_HYS

U

V

3

%

T

DEGLITCH

Deglitch Time

V

20

µs

ENABLE

V

EN

Enable Logic High Threshold

V

1.10

1.17

1.24

V

V

EN_HYS

Enable Hysteresis

V

100

mV

I

EN

Enable Pin Pull-Up Current

V

2

µA

FREQUENCY SYNCHRONIZATION

V

LH_SYNC

SYNC Pin Logic High

V

2.0

V

V

LL_SYNC

SYNC Pin Logic Low

V

0.8

V

SYNC

FSW_L

Minimum Clock Sync Frequency

200

kHz

SYNC

FSW_H

Maximum Clock Sync Frequency

1200

kHz

THERMAL SHUTDOWN

T

SHD

Thermal Shutdown

Temperature Rising

165

°C

T

SHD_HYS

Thermal Shutdown Hysteresis

Temperature Falling

15

°C

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor to each pin.

Note 3: VDD is the output of an internal linear regulator. Under normal operating conditions where VIN is greater than 5.5V, VDD must not be connected to any

external voltage source. In an application where VIN is between 3.0V and 5.5V, it is recommended to connect VDD to VIN. In order to have better noise rejection

under these conditions, a 1

Ω and 1µF RC input filter may be used.

Note 4: Tested on a four layer JEDEC board. Four vias are provided under the LLP exposed pad and nine vias are provided under the eTSSOP exposed pad.

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