ADC Data

ADC Frame Clock

ADC Clock

t

su

t

su

t

h

t

h

T0513-01

GC5330

GC5337

www.ti.com

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

Figure 21. RX ADC LVDS Timing Specifications (RXA and RXB)

Table 21. RXA-BB Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

RX input clock frequency

250

MHz

Input data setup time on port A before

160

ps

ADCA Clk transition

Input data hold time on port A after

200

ps

ADCA Clk transition

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

at

–40°C.

(2)

Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

310

MHz

DPD input clock frequency

{370}

250

BB internal clock frequency

MHz

{290}

DPD input clock duty cycle

40%

60%

2.5%

0.25

ns

0.1

ns

0.35

ns

0.05

ns

(1)

The PLL output ranges are 400

–1000 MHz. These are configuration dependent but related to the DPDCLK frequency. The cmd5330

software automatically checks these limits when compiling a configuration.

(2)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

at

–40°C.

(3)

Specification is from the PLL specification and is not production tested.

© 2010–2011, Texas Instruments Incorporated

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