PJDLLLC70

Very Low Capacitance Diode Array

SPECIFICATION FEATURES

APPLICATIONS

MAXIMUM RATINGS

Rating

Symbol

Value

Units

This diode array is configured to protect up to two high speed data

transmission lines, used in Low Voltage Differential Signal (LVDS) ports.

Acting as a line terminator, minimizes overshoot and undershoot conditions

due to bus impedance as well as protect against over-voltage events as

electrostatic discharges. The line-line concept minimizes the problems to

customers to re-route PCB lines, simplifying the design.

Maximum Capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground

Industry Standard SMT Package SOT563

Maximum Leakage Current of 1µA @ VRWM

USB 2.0 and Firewire Port Protection

HDMI Version 1.3

Peak Pulse Current (8/20µs Waveform)

Rectifier Repetitive Peak Reverse Voltage

Operating Junction Temperature Range

Storage Temperature Range

Soldering Temperature, t max = 10s

7/23/2009

Page 1

www.panjit.com

12

A

V

70

°C

-55 to +125

°C

-55 to +150

°C

260

I

V

T

T

T

PPM

L

RRM

stg

Tj = 25°C Unless otherwise noted

DVI

IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact*

100% Tin Matte finish (LEAD-FREE PRODUCT)

J

Gnd

+VREF

Line1

Line2

Line1

Line2

SOT563 Package

1

2

3

4

6

5

GND

+VREF

I/O Line 1

I/O Line 2

GND

+VREF

I/O Line 1

I/O Line 2

Note: ESD Testing requires to connect a TVS between +VREF and GND, if there is no +VREF Bias connected.

Line-line concept ease the PCB design, directly placing the device over

the data lines, opening only the contact points. VREF is fixed by the

operating voltage, referenced to the ground.

Note: pins 1and 6 (Line1) as well as pins 3

and 4 (Line2) must be connected

externally, as the drawing attached below.

12

3

4

5

6

4

1

2

3

6

5

MARKING : 70