MPC5673F datasheet(43/132 Pages) FREESCALE

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Electrical Characteristics

MPC5674F Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

4.11

AC Specifications

4.11.1

Clocking

The Figure 16 shows the operating frequency domains of various blocks on MPC5674F.

Figure 16. MPC5674F Block Operating Frequency Domain Diagram

Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see

Table 29 and Table 30 for descriptions of bit settings).

5 For maximum flash performance, set to 0b1.

6 This is the nominal maximum frequency of operation in Enchanced Mode. Max speed is the maximum speed

allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system core clock(fsys)+ 2% FM

and 132 Mhz platform clock (fplatf)+ 2% FM.

7 Preliminary setting. Final setting pending characterization.

PLL

CORE

PLATFORM /

eTPU /

EBI

CAL BUS

EXTAL

D_CLKOUT

fplatf

Note: tcycsys = 1 / fsys

tcyc =1 / fplatf

÷ 2 = divide-by-2

÷ X = divide-by-X, depending on SIU_SYSDIV[BYPASS]

and SIU_SYSDIV[SYSCLKDIV].

BLOCKS /

(D_CLKOUT is not available

on all packages and cannot

be programmed for faster

than fsys/2.)

÷ 2

PLLCFG[0:1]

SIU_SYSDIV[SYSCLKDIV[0:1]]

IPG DIV SEL

ETPU DIV SEL

SIU_SYSDIV[IPCLKDIV[0:1]]

fetpu

SYSDIV

÷ X

FLASH

NDEDI

DIV

febi_cal

SIU_SYSDIV[BYPASS]

X = 2, 4, 8, or 16

X=1

fsys

SIU_ECCR[EBDF[0:1]]

fperiph

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