MPC8360E datasheet(7/108 Pages) FREESCALE

7 / 108 page

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

•

PCI interface

— PCI Specification Revision 2.3 compatible

— Data bus widths:

– Single 32-bit data PCI interface that operates at up to 66 MHz

— PCI 3.3-V compatible (not 5-V compatible)

— PCI host bridge capabilities on both interfaces

— PCI agent mode supported on PCI interface

— Support for PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses and support for delayed read transactions

— Support for posting of processor-to-PCI and PCI-to-memory writes

— On-chip arbitration, supporting five masters on PCI

— Support for accesses to all PCI address spaces

— Parity support

— Selectable hardware-enforced coherency

— Address translation units for address mapping between host and peripheral

— Dual address cycle supported when the device is the target

— Internal configuration registers accessible from PCI

•

Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller

— Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

•

Programmable interrupt controller (PIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for 8 external and 35 internal discrete interrupt sources

— Support for one external (optional) and seven internal machine checkstop interrupt sources

— Programmable highest priority request

— Four groups of interrupts with programmable priority

— External and internal interrupts directed to communication processor

— Redirects interrupts to external INTA pin when in core disable mode

— Unique vector number for each interrupt source

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