Pin 5

GND

Schematic for V

CC

Pin 2

45

Pin 7

GND

Schematic for CLK Line

100

Pin 6,8

GND

Schematic for DATA1, DATA2 Lines

Pin 1,3

TPD3F303

SLVSAM5 – JANUARY 2011

www.ti.com

CIRCUIT DIAGRAMS

TERMINAL FUNCTIONS

TERMINAL

TYPE

DESCRIPTION

DPV/DQD

NAME

PIN NO.

Data and Rest signals Input, Output pins. The DATA1 and DATA2 are symmetric circuits.

DATAx_IN,

Input, Output

1, 3, 6, 8

They can be used interchangeably for either DATA or RESET pins based off board layout

DATAx_OUT

Pins

scheme.

CLK_OUT,

Input, Output

2, 7

Clock Input and Output signals.

CLK_IN V

Pins

5

NC

4

No Connect

Not connected to any internal circuit. Leave this pin floating.

Central ground

Ground connection for the EMI filter. It is very important to connect the device GND to the

GND

Ground

Pad

printed circuit board ground plane through Vias directly under the package.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

IO voltage tolerance

IO pins

5.5

V

Operating free-air temperature range

–40

85

°C

Storage temperature range

–55

155

°C

IEC 61000-4-2 Contact Discharge

IO pins

±15

KV

IEC 61000-4-2 Air-gap Discharge

IO pins

±15

KV

Human Body Model ESD

IO pins

±15

KV

(1)

Stresses beyond those listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of

the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Clamp voltage

IO pin to ground

±10

V

Leakage current

IO pin to ground

0.1

µA

CLK series resistors

40

47

55

Ω

Data/RST series resistors

85

100

115

Ω

IO Capacitance

IO Pins to GND

16

20

24

pF

Break-down Voltage

6

V

–3 dB BW for DATA/RESET line

294

MHz

2

Submit Documentation Feedback

Copyright © 2011, Texas Instruments Incorporated

Product Folder Link(s): TPD3F303