TABLE 1

DATABUS

SELECTED REGISTER

CS/

RS2

RS1

RS0

RD/ WR/

REGISTER

MAP

OPERATION

1

x

x

x

x

x

none

none

none

0

0

0

0

0

1

MCR0

DBL

READ

0

0

0

1

0

1

MCR1

DBL

READ

0

0

1

0

0

1

ODR0

DBL

READ

0

0

1

1

0

1

ODR1

DBL

READ

0

1

0

0

0

1

ODR2

DBL

READ

0

1

0

1

0

1

ODR3

DBL

READ

0

1

1

0

0

1

STR

DBL

READ

0

0

0

0

1

0

MCR0

DBL

WRITE

0

0

0

1

1

0

MCR1

DBL

WRITE

0

0

1

0

1

0

IDR0

DBL

WRITE

0

0

1

1

1

0

IDR1

DBL

WRITE

0

1

0

0

1

0

IDR2

DBL

WRITE

0

1

0

1

1

0

IDR3

DBL

WRITE

0

1

1

0

1

0

TCR

DBL

WRITE

TABLE 2

DATABUS

SELECTED REGISTER

CS/

RS2

RS1

RS0

RD/ WR/

REGISTER

MAP

OPERATION

1

x

x

x

x

x

none

none

none

0

0

0

0

0

1

[MCR1:MCR0]

[DBH:DBL]

READ

0

0

1

0

0

1

[ODR1:ODR0]

[DBH:DBL]

READ

0

1

0

0

0

1

[ODR3:ODR2]

[DBH:DBL]

READ

0

1

1

0

0

1

[STR]

[DBL]

READ

0

0

0

0

1

0

[MCR1:MCR0]

[DBH:DBL]

WRITE

0

0

1

0

1

0

[IDR1:IDR0]

[DBH:DBL]

WRITE

0

1

0

0

1

0

[IDR3:IDR2]

[DBH:DBL]

WRITE

0

1

1

0

1

0

[TCR]

[DBL]

WRITE

Note 1. x indicates don’t care case.

Note 2. DBL stands for DB <7:0> ; DBH stands for DB <15:8>.

7766-111406-5

I/O PINS: The following is a description of the input/out pins.

RS0, RS1, RS2

Inputs. These three inputs select the hardware registers for read/write access according to Table 1 and Table 2.

Table 1 applies to Octal bus configuration. Table 2 applies to Hex bus configuration.