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CY2DM1502 데이터시트(PDF) 1 Page - Cypress Semiconductor

부품명 CY2DM1502
상세설명  1:2 CML / LVPECL Input to CML Output Fanout Buffer
PDF  12 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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CY2DM1502
1:2 CML / LVPECL Input to CML Output
Fanout Buffer
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 001-56315 Rev. *F
Revised February 25, 2011
Features
■ One current mode logic (CML) or low-voltage positive
emitter-coupled logic (LVPECL) input pair distributed to two
CML output pairs
■ 20-ps maximum output-to-output skew
■ 480-ps maximum propagation delay
■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
■ Up to 1.5 GHz operation
■ 8-Pin thin shrunk small outline package (TSSOP) package
■ 2.5-V or 3.3-V operating voltage
[1]
■ Commercial and industrial operating temperature range
Functional Description
The
CY2DM1502
is
an
ultra-low
noise,
low-skew,
low-propagation delay 1:2 CML or LVPECL to CML fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The device has a fully differential
internal architecture that is optimized to achieve low additive jitter
and low skew at operating frequencies of up to 1.5 GHz.
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Logic Block Diagram
Q0
Q0#
Q1
Q1#
IN
IN#
VDD
VSS
VDD
[+] Feedback


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