Analog Integrated Circuit Device Data

Freescale Semiconductor

21

33886

5.0 A H-BRIDGE

THERMAL ADDENDUM - REVISION 2.0

5.0 A H-BRIDGE

THERMAL ADDENDUM - REVISION 2.0

Introduction

This thermal addendum is provided as a supplement to the MC33186

technical data sheet. The addendum provides thermal performance information

that may be critical in the design and development of system applications. All

electrical, application, and packaging information is provided in the data sheet.

Packaging and Thermal Considerations

The MC33186 is offered in a 20 pin HSOP exposed pad, single die package.

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not

meant to and will not predict the performance of a package in an application-

specific environment. Stated values were obtained by measurement and

simulation according to the standards listed below.

Standards

NOTES:

1.Per JEDEC JESD51-2 at natural convection, still air condition.

2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7.

3.Per JEDEC JESD51-8, with the board temperature on the center

trace near the center lead.

4.Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5.Thermal resistance between the die junction and the exposed

pad surface; cold plate attached to the package bottom side,

remaining surfaces insulated.

Figure 24. Thermal Land Pattern for Direct Thermal

Attachment According to JESD51-5

20-PIN

HSOP-EP

33886

Note For package dimensions, refer to

the 33886 device data sheet.

DH SUFFIX

VW (Pb-FREE) SUFFIX

98ASH70702A

20-PIN HSOP-EP

=

.

P

Table 6.

Thermal Performance Comparison

Thermal Resistance

[°C/W]

(1)(2)

20

(2)(3)

6.0

(1)(4)

52

(5)

1.0

1.0

1.0

0.2

0.2

Soldermast

openings

Thermal vias

connected to top

buried plane

* All measurements

are in millimeters

20 Terminal HSOP-EP

1.27 mm Pitch

16.0 mm x 11.0 mm Body

12.2 mm x 6.9 mm Exposed Pad