PIC12F752 datasheet(78/204 Pages) MICROCHIP

78 / 204 page

PIC12F752/HV752

DS41576A-page 78

Preliminary

 2011 Microchip Technology Inc.

10.2.5

COMPARE DURING SLEEP

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

TABLE 10-3:

SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

CCP1CON

—

DC1B<1:0>

CCP1M<3:0>

CCPR1L

Capture/Compare/PWM Register 1 Low Byte (LSB)

CCPR1H

Capture/Compare/PWM Register 1 High Byte (MSB)

INTCON

GIE

PEIE

T0IE

INTE

IOCIE

T0IF

INTF

IOCIF

PIE1

TMR1GIE

ADIE

—

HLTMR1IE

TMR2IE

TMR1IE

PIE2

—

C2IE

C1IE

—

COG1IE

—

CCP1IE

PIR1

TMR1GIF

ADIF

—

HLTMR1IF

TMR2IF

TMR1IF

PIR2

—

C2IF

C1IF

—

COG1IF

—

CCP1IF

T1CON

TMR1CS<1:0>

T1CKPS<1:0>

Reserved

T1SYNC

—TMR1ON

T1GCON

TMR1GE

T1GPOL

T1GTM

T1GSPM

T1GGO/DONE

T1GVAL

T1GSS<1:0>

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

57*

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

57*

TRISA

—

TRISA5

TRISA4

TRISA3(1)

TRISA2

TRISA1

TRISA0

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

Page provides register information.

Note

TRISA3 always reads ‘1’.

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