Micrel Inc.

MICRF221

October 2008

2

M9999-100108

(408) 955-1690

Pin Configuration

Figure 2. MICRF221AYQS Pin Configuration

Pin Description

16-Pin

QSOP

Pin

Name

Pin Function

1

RO1

Reference Oscillator (input): Reference resonator input connection to pierce oscillator stage. May also

be driven by external reference signal of 1.5V p-p amplitude maximum. 7pF to GND during normal

operation.

2

GNDRF

Negative supply connection associated with ANT RF input.

3

ANT

Antenna (input): RF signal input from antenna. Internally AC coupled. It is recommended a matching

network with an inductor-to-RF ground be used to improve ESD protection.

4

GNDRF

Negative supply connection associated with ANT RF input.

5

Vdd

Positive supply connection for all chip functions.

6

SQ

Squelch control logic input with an active internal pull-up when not shut down. Low to reverse level set

by serial interface bit D17. Low enables squelch for default SIF register.

7

SEL0

Select (input): Logic control input with active 3μA (8μA max) internal pull-up when not in shutdown or

SLEEP mode. It does not need to be defined in SLEEP mode. Used in conjunction with SEL1 to control

D3 bandwidth LSB when serial interface contains default setting.

8

SHDN

Shutdown logic control input. Active internal pull-up.

9

GND

Negative supply connection for all chip functions except for RF input.

10

DO

Demodulated data (output): May be blanked until bit checking test is acceptable. A current limited

CMOS output during normal operation this pin is also used as a CMOS Schmitt input for serial interface

data. A 25kΩ pull-down is present when device is in shutdown and sleep modes.

11

SEL1

Select (input): Logic control input with active 3μA (8μA max) internal pull-up when not in shutdown or

SLEEP mode. It does not need to be defined in SLEEP mode. Used in conjunction with SEL0, to control

D4 bandwidth MSB, when serial interface contains default setting.

12

CTH

Demodulation threshold voltage integration capacitor. Capacitor-to-GND sets the settling time for the

demodulation data slicing level. Values above 1nF are recommended and should be optimized for data

rate and data profile.

13

CAGC

AGC filter capacitor. A capacitor, normally greater than 0.47μF, is connected from this pin-to-GND

14

RSSI

Received signal strength indication (output): Output is from a switched capacitor integrating op amp

with 220Ω typical output impedance.

15

SCLK

Serial interface input clock. CMOS Schmitt input. A 25kΩ pull-down is present when device is in

shutdown mode.

16

RO2

Reference resonator connection. 7pF to GND during normal operation.

1

RO1

GNDRF

ANT

GNDRF

Vdd

SQ

SEL0

SHDN

16 RO2

SCLK

RSSI

CAGC

CTH

SEL1

DO

GND

15

14

13

12

11

10

9

2

3

4

5

6

7

8