R5F52107ADFN datasheet(39/92 Pages) RENESAS

39 / 92 page

R01DS0041EJ0050 Rev.0.50

Page 39 of 90

Apr 15, 2011

RX210 Group

2. CPU

Under development Preliminary document

Specifications in this document are tentative and subject to change.

Table 2.5

16-Bit Read Operations when Little Endian has been Selected

Operation

Address

of src

Reading

a 16-bit unit from

address 0

Reading

a 16-bit unit from

address 1

Reading

a 16-bit unit from

address 2

Reading

a 16-bit unit from

address 3

Reading

a 16-bit unit from

address 4

Reading

a 16-bit unit from

address 5

Reading

a 16-bit unit from

address 6

Address 0

Transfer to LL

——————

Address 1

Transfer to LH

Transfer to LL

—————

Address 2

—

Transfer to LH

Transfer to LL

————

Address 3

—

Transfer to LH

Transfer to LL

—

Address 4

—

Transfer to LH

Transfer to LL

—

Address 5

————

Transfer to LH

Transfer to LL

—

Address 6

—————

Transfer to LH

Transfer to LL

Address 7

——————

Transfer to LH

Table 2.6

16-Bit Read Operations when Big Endian has been Selected

Operation

Address

of src

Reading

a 16-bit unit from

address 0

Reading

a 16-bit unit from

address 1

Reading

a 16-bit unit from

address 2

Reading

a 16-bit unit from

address 3

Reading

a 16-bit unit from

address 4

Reading

a 16-bit unit from

address 5

Reading

a 16-bit unit from

address 6

Address 0

Transfer to LH

——————

Address 1

Transfer to LL

Transfer to LH

—————

Address 2

—

Transfer to LL

Transfer to LH

————

Address 3

—

Transfer to LL

Transfer to LH

—

Address 4

—

Transfer to LL

Transfer to LH

—

Address 5

————

Transfer to LL

Transfer to LH

—

Address 6

—————

Transfer to LL

Transfer to LH

Address 7

——————

Transfer to LL

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