IMX53AEC datasheet(65/178 Pages) FREESCALE

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Electrical Characteristics

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2

Freescale Semiconductor

Figure 29 and Table 41 show the address and control timing parameters for LPDDR2.

Figure 29. DDR SDRAM Address and Control Timing Parameters for LPDDR2

DDR4

CS, RAS, CAS, CKE, WE, ODT setup time

tIS

0.6

—

DDR5

CS, RAS, CAS, CKE, WE, ODT hold time

tIH

0.6

—

DDR6

Address output setup time

tIS

0.6

—

DDR7

Address output hold time

tIH

0.6

—

1 All timings are refer to Vref level cross point.

Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.

Table 41. DDR SDRAM Timing Parameter Table for LPDDR21 2

1 All timings are refer to Vref level cross point.

Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.

Parameter

Symbol

SDCLK = 400 MHz

Units

Min

Max

LP1

SDRAM clock high-level width

tCH

0.45

0.55

tCK

LP2

SDRAM clock low-level width

tCL

0.45

0.55

tCK

LP3

CS, CKE setup time

tIS

0.3

—

LP4

CS, CKE hold time

tIH

0.3

—

LP3

CA setup time

tIS

0.3

—

LP4

CA hold time

tIH

0.3

—

Table 40. DDR SDRAM Timing Parameter Table1 2 (continued)

Parameter

Symbol

SDCLK = 400 MHz

Units

Min

Max

CKE

LP4

LP3

LP4

LP3

LP2

LP3

LP1

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