전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AD9146 데이터시트(PDF) 21 Page - Analog Devices

부품명 AD9146
상세설명  Dual, 16-Bit, 1230 MSPS, TxDAC Digital-to-Analog Converter
PDF  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9146 데이터시트(HTML) 21 Page - Analog Devices

Back Button AD9146 Datasheet HTML 17Page - Analog Devices AD9146 Datasheet HTML 18Page - Analog Devices AD9146 Datasheet HTML 19Page - Analog Devices AD9146 Datasheet HTML 20Page - Analog Devices AD9146 Datasheet HTML 21Page - Analog Devices AD9146 Datasheet HTML 22Page - Analog Devices AD9146 Datasheet HTML 23Page - Analog Devices AD9146 Datasheet HTML 24Page - Analog Devices AD9146 Datasheet HTML 25Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 52 page
background image
AD9146
Rev. 0 | Page 21 of 52
Register
Name
Address
(Hex)
Bits
Name
Description
Default
Clock
Receiver
Control
0x08
7
DACCLK duty correction
1 = enable duty cycle correction on the DACCLK input.
0
6
REFCLK duty correction
1 = enable duty cycle correction on the REFCLK input.
0
5
DACCLK cross-correction
1 = enable differential crossing correction on the DACCLK
input.
1
4
REFCLK cross-correction
1 = enable differential crossing correction on the
REFCLK input.
1
PLL
Control
0x0A
7
PLL enable
1 = enable the PLL clock multiplier. The REFCLK input is
used as the PLL reference clock signal.
0
6
PLL manual enable
1 = enable manual selection of the VCO band. The correct
VCO band must be determined by the user and written to
Bits[5:0].
1
[5:0]
Manual VCO Band[5:0]
Selects the VCO band to be used.
000000
0x0C
[7:6]
PLL Loop Bandwidth[1:0]
Selects the PLL loop filter bandwidth.
11
00 = widest bandwidth.
…
11 = narrowest bandwidth.
[4:0]
PLL Charge Pump
Current[4:0]
Sets the nominal PLL charge pump current.
10001
00000 = lowest current setting.
…
11111 = highest current setting.
0x0D
[7:6]
N2[1:0]
PLL control clock divider. This divider determines the ratio
of the DACCLK frequency to the PLL controller clock
frequency. fPC_CLK must always be less than 75 MHz.
11
00 = fDACCLK/fPC_CLK = 2.
01 = fDACCLK/fPC_CLK = 4.
10 = fDACCLK/fPC_CLK = 8.
11 = fDACCLK/fPC_CLK = 16.
4
PLL cross-control enable
1 = enable PLL cross-point controller.
1
[3:2]
N0[1:0]
PLL VCO divider. This divider determines the ratio of the
VCO frequency to the DACCLK frequency.
10
00 = fVCO/fDACCLK = 1.
01 = fVCO/fDACCLK = 2.
10 = fVCO/fDACCLK = 4.
11 = fVCO/fDACCLK = 4.
[1:0]
N1[1:0]
PLL loop divider. This divider determines the ratio of the
DACCLK frequency to the REFCLK frequency.
01
00 = fDACCLK/fREFCLK = 2.
01 = fDACCLK/fREFCLK = 4.
10 = fDACCLK/fREFCLK = 8.
11 = fDACCLK/fREFCLK = 16.
PLL Status
0x0E
7
PLL locked
1 = the PLL-generated clock is tracking the REFCLK input
signal.
N/A
[3:0]
VCO Control Voltage[3:0]
VCO control voltage readback. See Table 22.
N/A
0x0F
[5:0]
VCO Band Readback[5:0]
Indicates the VCO band currently selected.
N/A



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com