CY2DP1502ZXC datasheet(5/13 Pages) CYPRESS

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CY2DP1502

Document Number: 001-56308 Rev. *G

Page 5 of 13

AC Electrical Specifications

(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))

Parameter

Description

Condition

Min

Typ

Max

Unit

FIN

Input frequency

–

1.5

GHz

FOUT

Output frequency

FOUT = FIN

–

1.5

GHz

VPP

LVPECL differential output voltage

peak to peak, single-ended. terminated

with 50

 to V

DD – 2.0

[6]

Fout = DC to 150 MHz

600

–

Fout = >150 MHz to 1.5 GHz

400

–

tPD

[7]

Propagation delay input pair to output

pair

Input rise/fall time < 1.5 ns

(20% to 80%)

––

480

tODC

[8]

Output duty cycle

50% duty cycle at input

Frequency range up to 1 GHz

–

tSK1

[9]

Output-to-output skew

Any output to any output, with

same load conditions at DUT

––

tSK1 D

[9]

Device-to-device output skew

Any output to any output between

two or more devices. Devices

must have the same input and

have the same output load.

––

150

PNADD

Additive RMS phase noise

156.25-MHz Input

Rise/fall time < 150 ps (20% to 80%)

VID > 400 mV

Offset = 1 kHz

–

–120

dBc/Hz

Offset = 10 kHz

–

–130

dBc/Hz

Offset = 100 kHz

–

–135

dBc/Hz

Offset = 1 MHz

–

–145

dBc/Hz

Offset = 10 MHz

–

–153

dBc/Hz

Offset = 20 MHz

–

–155

dBc/Hz

tJIT

[10]

Additive RMS phase jitter (Random)

156.25 MHz, 12 kHz to 20 MHz

offset; input rise/fall time < 150 ps

(20% to 80%),

VID > 400 mV

–

0.15

tR, tF

[11]

Output rise/fall time

50% duty cycle at input,

20% to 80% of full swing

(VOL to VOH)

Input rise/fall time < 1.5 ns

(20% to 80%)

––

250

Notes

6. Refer to Figure 3 on page 6.

7. Refer to Figure 4 on page 6.

8. Refer to Figure 5 on page 6.

9. Refer to Figure 6 on page 7.

10. Refer to Figure 7 on page 7.

11. Refer to Figure 8 on page 7.

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